1. Field of the Invention
The present invention generally relates to manufacturing methods of a metal-insulator-semiconductor (MIS) device using trench isolation technique. More particularly, the present invention is directed to a method of manufacturing a MIS device such as a metal oxide semiconductor (MOS) type field effect transistor (FET) in which a gate electrode is formed to cover the upper portion of an element or device forming region which is isolated by a trench.
2. Description of the Prior Art
In general, there has been proposed a method of manufacturing such a MOS type FET as shown in FIG. 1 in which a gate electrode 22 is formed to cover the upper portion of an element or a device forming region which is isolated by a trench. A manufacturing process sequence for forming the MOS type FET shown in FIG. 1 will be explained with reference to FIGS. 2A to 2E which are sectional views of the MOS type FET taken along the line II--II in FIG. 1.
Referring to FIG. 2A, for example, portions of a p-type silicon substrate 23 serving as device isolation regions are partially etched away by the reactive ion etching (RIE) process, for example, thereby forming trenches 24. Portions of the p-type silicon substrate 23 other than the trenches 24 constitute an element or device forming region 21.
Thereafter, as shown in FIG. 2B, an SiO.sub.2 film 25 is formed on the entire surface of the p-type silicon substrate 23 by the bias electron cyclotron resonance (ECR) plasma chemical vapour deposition (CVD) technique.
Then, after forming a flattening film such as SOG or BPSG on the entire surface of the SiO.sub.2 film 25, the flattening film and the SiCO.sub.2 film 25 are etched back by the RIE process, for example, to thereby flatten the SiO.sub.2 film 25, as shown in FIG. 2C. This flattening process is continued until the device forming region 21 of the silicon substrate 23 is exposed. At this time, the SiO.sub.2 film 25 is buried in the trenches 24. In this case, there is such a portion in which the upper surface of the SiO.sub.2 film 25 is lower than the upper surface of the device forming region 21 of the silicon substrate 23 due to the scatterings of the etching back rate.
Next, as shown in FIG. 2D, the thermal oxidation process is carried out on the entire surface of the device forming region 21 and the SiO.sub.2 film 25 to thereby form a gate insulation film 26 made of a thermal oxidation film on the exposed surface of the silicon substrate 23, that is, the upper surface of the device forming region 21.
Thereafter, as shown in FIG. 2E, a polycrystalline silicon layer is formed on the entire surface of both the SiO.sub.2 film 25 and the gate insulation film 26, then the patterning process is carried out for the polycrystalline silicon layer to form a gate electrode 27, thereby providing a MOS type FET. In this case, the gate electrode 27 is formed to cover the upper portion of the device forming region 21.
However, in the conventional manufacturing method of a MOS type FET, after the SiO.sub.2 film 25 has been buried in the trenches 24, the thermal oxidation process is carried out therefor so as to form the gate insulation film 26 of the thermal oxidation film on the exposed portion of the silicon substrate 23 (upper surface of the device forming region 21), so that the gate insulation film 26 becomes thinner in thickness at edge portions a of the device forming region 21 of the silicon substrate 23, as shown in FIG. 2E. In particular, the thickness of the gate insulation film 26 is quite thin at the edge portion thereof adjacent to the edge of the SiO.sub.2 film 25 whose upper surface is lower than the upper surface of the device forming region 21 due to the scatterings of the etching back rate.
Further, in addition to the thin thickness of the gate insulation film 26, since the edge portions a of the device forming region 21 of the silicon substrate 23 are formed at substantially a right angle, the electrostatic concentration likely occurs at the edge portions a, thereby degrading or lowering a breakdown voltage of the gate electrode disadvantageously.
Furthermore, the stress is liable to be applied to the edge portions a during the manufacturing process of the MOS type FET, so that there appears lattice defect at the edge portions frequently. The lattice defect causes the faulty a leakage current, thereby degrading a yield of the MOS type FET remarkably.